1. Field of the Invention
The present invention relates to an integrated circuit device, for example, a semiconductor integrated circuit including a built-in self test circuit.
2. Background Art
There is widely used a method such as building a built-in self test circuit (hereinafter referred to as a “BIST circuit”) into a semiconductor integrated circuit having an embedded memory, and detecting a failure in the memory using the BIST circuit, in a manufacturing test on the semiconductor integrated circuit. Specific examples of a failure detection method include a “comparator-type BIST” in which read data is compared with written data after each reading, and the presence or absence of a failure is determined based on a comparison result, and a “compactor-type BIST” in which reading results are collectively compacted, and the presence or absence of a failure is determined based on a compaction result.
An operation clock of the BIST circuit needs to be synchronized with an operation clock of the memory. In particular, when high-speed test operation is performed, it is necessary to cause the clock of the BIST circuit and the clock of the memory to have the same source, and to perform adjustment processing such as clock tree synthesis to minimize clock skew.
In a multi-port memory having a plurality of ports, each port generally includes its own clock input which is supplied with a clock. In some cases, these ports are supplied with clocks with frequencies independent of each other. In such cases, if no measures are taken, it is impossible to synchronize an operation clock of a BIST circuit with clocks of all these ports, and it is impossible to proceed with a test correctly. In order to synchronize the operation clock of the BIST circuit with the clocks of the ports, the clock input of each port may be provided with a switching circuit so that, in a test, the ports are supplied with the clocks having the same source. However, the speed of the operation clock of the multi-port memory is often high, and insertion of such a switching circuit largely affects the performance of the multi-port memory. Insertion of such a switching circuit is also disadvantageous in that it disables a test at a clock frequency of a system clock.
JP-A 2003-217299 (KOKAI) discloses a circuit configuration which performs a test using a BIST circuit without a switching circuit. In JP-A 2003-217299 (KOKAI), after writing into all addresses of a memory is performed in response to a first clock, reading from all the addresses of the memory is performed in response to a second clock. However, this is the simplest among algorithms for a test using a BIST circuit, and a more complicated algorithm is generally used, such as a “March test” in which writing and reading are alternately performed for each address. In a test based on such a complicated algorithm, port switching is frequently performed during operation, therefore the circuit configuration in JP-A 2003-217299(KOKAI) cannot perform such a test.